Title :
Pedestrian detection implemented on a fixed-point parallel architecture
Author :
Wilson, Tom ; Glatz, Michael ; Hödlmoser, Michael
Author_Institution :
Image Process. Group, Visual8 Syst., Vienna, Austria
Abstract :
This paper describes the implementation of a real-time pedestrian detector on a single instruction, multiple data (SIMD), fixed-point digital signal processor (DSP). We reformulate the Histogram of Oriented Gradients algorithm for calculation with a relatively simple instruction set architecture (ISA) and partition the image for parallel processing. Results obtained using an ISA simulator indicate a maximum frame rate above 40 fps for 1 MPixel images, with a detection accuracy comparable to a double-precision floating-point reference implementation.
Keywords :
digital signal processing chips; field programmable gate arrays; floating point arithmetic; image motion analysis; object detection; parallel processing; FPGA; ISA simulator; SIMD processor; double-precision floating-point reference implementation; fixed-point digital signal processor; fixed-point parallel processor; histograms of oriented gradients algorithm; image partitioning; instruction set architecture; real-time pedestrian detector; Cameras; Hardware; Histograms; Object detection; Parallel architectures; Parallel processing; Partitioning algorithms; Signal processing algorithms; Support vector machine classification; Support vector machines; Driver Assistance; Embedded Computer Vision; Object Detection; Parallel Processing; SIMD;
Conference_Titel :
Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-2975-2
Electronic_ISBN :
978-1-4244-2976-9
DOI :
10.1109/ISCE.2009.5156970
