Title :
Cell Broadband Engine Processor Design Methodology
Author :
Takahashi, Osamu ; Behnen, E. ; Cottier, S.R. ; Coulman, P. ; Dhong, Sang H. ; Flachs, B. ; Hofstee, Peter ; Johnson, C.J. ; Posluszny, S.
Author_Institution :
IBM, Austin
Abstract :
The cell BE design methodology is described which enables high frequency, high performance, power efficient, and area optimized design. It includes a hierarchical design style, clean clock boundary, effective use of non-scan latches, at-speed scan testing, custom design like synthesized macro, fine grained clock gating scheme, and cycle accurate power analysis.
Keywords :
integrated circuit design; integrated circuit testing; microprocessor chips; area optimized design; at-speed scan testing; cell broadband engine processor; clean clock boundary; cycle accurate power analysis; fine grained clock gating; hierarchical design style; high frequency design; high performance design; nonscan latches; power efficient design; Clocks; DH-HEMTs; Delay; Design methodology; Design optimization; Engines; Frequency; Process design; Solid state circuit design; USA Councils;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405830
