Riley, M. ; Flachs, B. ; Dhong, S. ; Gervais, G. ; Weitzel, S. ; Wang, M. ; Boerstler, D. ; Bolliger, M. ; Keaty, J. ; Pille, J. ; Berry, R. ; Takahashi, O. ; Nishino, Y. ; Uchino, T.
Author_Institution :
IBM, Austin
fYear :
2007
fDate :
16-19 Sept. 2007
Firstpage :
717
Lastpage :
720
Abstract :
The first generation cell broadband engine processor introduced the cell architecture that consists of nine processor cores fabricated in the 90 nm CMOS SOI technology. This paper describes the advances made by moving the cell broadband engine design from 90 nm CMOS SOI to 65 nm CMOS SOI.
Keywords :
CMOS digital integrated circuits; microprocessor chips; CMOS SOI technology; cell architecture; cell broadband engine processor; size 65 nm; CMOS process; CMOS technology; Circuits; Clocks; Computer architecture; Engines; Frequency; Random access memory; Silicon on insulator technology; Voltage;
