Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation

Slice-and-stack representation of a vertical substrate impurity profile in F-matrix computation captures isolation effects of deep N-wells as well as guard rings in chip-level substrate coupling. A reference flow of substrate noise analysis combines the derived equivalent circuit model of chip-level substrate coupling with a generalized model of noise injection from digital circuits due to gate switching operation. The flow is tightly united with a reference test-chip structure for on-chip substrate noise measurements, providing a basis for verification of design guidelines against substrate coupling in a given manufacturing technology. It is elucidated that the models of substrate noise coupling in twin-tub and triple-well designs are dominated by the leakage of Vss noise and capacitive coupling from Vdd noise, respectively, from measurements and analysis of a reference test chip in a 0.18-mum CMOS p-type bulk technology.