Yield analysis for fault-tolerant arrays

A technique for evaluating alternative cell implementations for use in arrays (RAM, ROM, PLA, etc.) with redundancy in order to select the array cell with the lowest manufacturing cost or highest yield is described. This selection is particularly important in yield-sensitive applications such as wafer-scale integration. Alternative cell implementations include different cell topologies and design rule scaling. The analysis is performed using the VLASIC catastrophic fault yield simulator. Using a redundant CMOS static random access memory as an example, it is shown that the cell with the lowest manufacturing cost for a nonredundant array does not necessarily have the lowest manufacturing cost for a redundant array. It is also shown that in a redundant array, neither the highest-yielding cell nor the smallest cell necessarily has the lowest manufacturing cost