DocumentCode :
2417335
Title :
Dynamically reconfigurable VLD circuit
Author :
Komoku, Kiyotaka ; Miyake, Takashi ; Morishita, Takayuki ; Sasaki, Nobuo
Author_Institution :
Dept. Commun. Eng., Okayama Prefectural Univ., Soja, Japan
fYear :
2009
fDate :
25-28 May 2009
Firstpage :
225
Lastpage :
227
Abstract :
A dynamically reconfigurable VLD (variable length decode) circuit is proposed. In this circuit, several comparators decode at input bitstream in parallel. Furthermore it can also decode next code in same time, using some comparators. The rate of number of comparators used for parallel and next code decoding is variable and the reconfiguration can be executed dynamically.
Keywords :
comparators (circuits); decoding; variable length codes; VLD circuit; comparators; dynamically reconfigurable circuit; next code decoding; parallel decoding; variable length decode; Circuits; Consumer electronics; Data compression; Decoding; Detectors; Digital audio players; Encoding; Energy consumption; Statistics; Throughput; VLD; reconfigurable; variavle length decode;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-2975-2
Electronic_ISBN :
978-1-4244-2976-9
Type :
conf
DOI :
10.1109/ISCE.2009.5157031
Filename :
5157031
Link To Document :
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