A 12-bit 100-MSps pipelined-SAR ADC with a time-interleaved second-stage

Author

Xiaoying Shen ; Hao Zhou ; Huabin Chen ; Fan Ye ; Ning Li ; Junyan Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

In this paper, a 12-bit 100-MS/s pipelined-SAR ADC is presented. The design properly selects the resolution of the two pipeline stages and adopts time-interleaving technique to improve the speed. A split-capacitor DAC in 2^nd-satge SAR ADC and a “half gain” residue amplifier minimize the power dissipation. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 11.2b near the Nyquist input frequency at the sampling rate of 100MS/s. The power consumption is only 8.6mW with the supply voltage of 1.2V and the FoM is 36.6fJ/conv.-step operating at 100MS/s.

Keywords

CMOS integrated circuits; amplifiers; analogue-digital conversion; capacitors; power consumption; CMOS technology; ENOB; FoM; Nyquist input frequency; half gain residue amplifier; pipelined-SAR ADC; power 8.6 mW; power consumption; power dissipation minimization; sampling rate; size 65 nm; speed improvement; split-capacitor DAC; successive approximation register ADC; supply voltage; time-interleaved second-stage design; voltage 1.2 V; word length 12 bit; Abstracts; Hardware; Signal to noise ratio; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021298

Filename

7021298