Recent advances in high-k dielectrics and inter layer engineering

State-of-the-art CMOS technology relies on the integration of multi-layer high-k/metal gate stacks in order to achieve high capacitance density while fulfilling the requirements in terms of gate leakage current density, interface state density, channel mobility, threshold voltage and reliability. Conventional SiO_x/HfO₂ gate dielectric stacks are capable of meeting the performance targets of current technology nodes and have been shown to possess sufficient short-term scalability, but solutions providing enhanced long-term scalability are actively researched, mostly via integration of higher-k oxides or high-k interfacial layers. This paper provides an overview of recent research efforts in this area, focusing on integration of high-k interfacial layers. We then analyze the potential scalability improvement which can be obtained through integration of thulium silicate as interfacial layer and summarize the main results supporting its applicability to future technology nodes.