Ge gate-all-around FETs on Si

Author

Liu, C.W. ; I-Hsieh Wong ; Yen-Ting Chen ; Wen-Hsien Tu ; Shih-Hsien Huang ; Shu-Han Hsu

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

High performance Ge inversion (INV) and junctionless (JL) gate-all-around (GAA) FETs are demonstrated on epi-Ge layer on SOI. The anisotropic etching is used to remove the defect near the Ge/Si interface and to form gate-all-around structure. The INV and JL pGAAFETs have I_on of 235 μA/μm and 270 μA/μm at V_GS - V_T = -2 V and V_DS = -1 V, respectively, and show good subthreshold characteristics. The (111) sidewall INV nFETs show 2X enhanced I_on of 110 μA/μm with respect to the devices with near (110) sidewalls.

Keywords

elemental semiconductors; etching; germanium; junction gate field effect transistors; power field effect transistors; silicon-on-insulator; Ge-Si; JL pGAA FET; SOI; anisotropic etching; defect removal; high performance inversion; ion enhancement; junctionless gate-all-around FET structure; sidewall INV nFET; subthreshold characteristics; voltage -1 V; voltage -2 V; Abstracts; Field effect transistors; Germanium silicon alloys; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021333

Filename

7021333