Title :
A LO generation system with optimized AFC scheme for multimode GNSS receivers
Author :
Songting Li ; Jiancheng Li ; Xiaochen Gu ; Hongyi Wang ; Zhaowen Zhuang
Author_Institution :
Coll. of Electron. Sci. & Eng., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
This paper presents a LO generation system used in multimode global navigation satellite system (GNSS) receivers in 55 nm CMOS. This system contains two PLL frequency synthesizers (FS) and supports simultaneous receiving of any two bands among GPS/GLONASS/Galileo/Compass systems with a flexible frequency plan. An optimized automatic frequency calibration (AFC) scheme using an error compensation logic enables fast and high-precision calibration process for optimum PLL operation. Measured results show that the phase noise of each FS is lower than -83 dBc/Hz and -110 dBc/Hz at 10 KHz and 1 MHz offset, respectively. And the locking time including AFC time and PLL time is only about 20 μs. The loop bandwidth varies by less than 6% for all GNSS signals and reference frequencies (10-80 MHz). Each FS consumes about 12 mA current from a 1.2 V supply, and the area of LO generation system is about 1.25 mm2.
Keywords :
CMOS integrated circuits; calibration; error compensation; frequency synthesizers; phase locked loops; radio receivers; radiofrequency integrated circuits; satellite navigation; CMOS technology; FS; GPS-GLONASS-Galileo-Compass system; Global Navigation Satellite system; LO generation system; PLL frequency synthesIzer; error compensation logic; frequency 10 MHz to 80 MHz; multimode GNSS receiver; optimized AFC scheme; optimized automatic frequency calibratIon scheme; size 55 nm; voltage 1.2 V; Amplitude modulation; CMOS integrated circuits; Global Positioning System; Mixers; Resonant frequency; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021361