Design of D flip-flops with low power-delay product based on FinFET

In this paper, FinFET has been introduced to the design of high performance D flip-flops. Based on the excellent electrical properties of FinFET, the SG-mode D flip-flop modified from original PHLFF by substituting SG-mode FinFET for planar MOSFET has a tremendous reduction of 87.0% on power-delay product (PDP). Considering the unique merits of multiple operating modes of FinFET, further optimization based on SG-mode PHLFF has been proposed to achieve lower PDP and more efficient area utilization rate. The simulation results indicate that the multi-mode PHLFF reduces the PDP by 92.6% and slightly decreases the number of transistors.