• DocumentCode
    2418831
  • Title

    A 3D HDI ASP: a cost-effective alternative to WSI signal processors

  • Author

    Warren, K.D. ; Reche, J.H. ; Jacobi, W.J. ; Lea, R.M.

  • Author_Institution
    Brunel Univ., Uxbridge, UK
  • fYear
    1989
  • fDate
    3-5 Jan 1989
  • Firstpage
    267
  • Lastpage
    276
  • Abstract
    A research project, in which various high-density interconnect (HDI) and wafer-scale integration (WSI) implementation variants of a common computer architecture, the associative string processor (ASP), are compared, is discussed. The ASP is a fault-tolerant and highly versatile massively parallel processor capable of sustaining high performance over a wide range of computationally intensive tasks and, unlike most other computer architectures, the ASP has been designed to exploit state-of-the-art microelectronic technology. The study indicates that, until the feasibility of WSI ASP technology has been proven, a 3-D HDI ASP seems to offer a cost-effective alternative technology for the development of highly compact massively parallel processors for aerospace and automotive applications
  • Keywords
    VLSI; computer architecture; digital signal processing chips; parallel processing; 3-D HDI ASP; associative string processor; computer architectures; high-density interconnect; massively parallel processor; wafer-scale integration; Application specific processors; Assembly; Ceramics; Collaboration; Computer architecture; Concurrent computing; Microelectronics; Signal processing; Substrates; Ultra large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-9901-9
  • Type

    conf

  • DOI
    10.1109/WAFER.1989.47557
  • Filename
    47557