Novel 1T-dram with fin-gate and pillar structure for hole storage and data retention time improvement

In this paper, we propose a novel SOI-based double-gate MOSFET with pillar structure for capacitorless one transistor dynamic random access memory (1T-DRAM) application, which has Fin-gate and Bottom-Gate, and we name it as the FBG 1T-DRAM. The proposed FBG 1T-DRAM cell has an additional storage region, which can increase the holes storage. In terms of the memory performance, we obtained about 61.4 μA/μm for the programming window and 204 ms for the data retention time. Furthermore, the device fabrication process has no self-aligned problems and is fully compatible with the conventional CMOS technology.