• DocumentCode
    2419080
  • Title

    Inductive coupling aware explicit cross-talk and delay formula for on-chip VLSI RLCG interconnects using difference model approach

  • Author

    Kar, Rajib ; Maheshwari, V. ; Choudhary, Aman ; Singh, Abhishek ; Mal, Ashis K. ; Bhattacharjee, A.K.

  • Author_Institution
    Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Durgapur, India
  • fYear
    2010
  • fDate
    29-31 July 2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper we have proposed a closed form delay and cross-talk noise formula for on-chip VLSI interconnect in the presence of inductive coupling. Inductive coupling effect has become an important issue in high frequency multi-layered VLSI interconnection systems. We first analytically derived the amount of crosstalk noise that would be induced on the quite victim line due to the transiting aggressor line. From that we have proposed an efficient model to estimate the on-chip interconnect delay in the presence of inductive coupling. We also have analytically shown the effect of inductive coupling onto the victim line. On-chip inductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. This paper proposes a difference model approach to derive crosstalk in the transform domain. A closed form solution for crosstalk is obtained by incorporating initial conditions using difference modal approach for distributed RLCG Interconnects. An inefficient evaluation of the crosstalk could be at the origin of a malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor or attacker nets and victim nets. The attacker net carries a signal that couples to the victim net through the parasitic capacitance. To determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. The comparison made between the results obtained by using our formula and that of SPICE, justifies the effectiveness of our approach.
  • Keywords
    SPICE; VLSI; crosstalk; integrated circuit interconnections; SPICE; crosstalk noise; difference model approach; inductive coupling aware explicit cross-talk; on-chip VLSI RLCG interconnects; Capacitance; Couplings; Crosstalk; Delay; Inductance; Integrated circuit interconnections; Mathematical model; Crosstalk; Delay Calculation; Difference Model; Distributed RLCG; Inductive Coupling; On-Chip Interconnect;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computing Communication and Networking Technologies (ICCCNT), 2010 International Conference on
  • Conference_Location
    Karur
  • Print_ISBN
    978-1-4244-6591-0
  • Type

    conf

  • DOI
    10.1109/ICCCNT.2010.5591802
  • Filename
    5591802