The pattern engineering before wafer bonding in smart-cut SOI for high voltage applications

A new silicon-on-insulator device with high voltage structure employing patterned buried oxide layer is proposed in this paper. In this structure, the buried layer is made of two dielectrics, one of which is SiO₂ and the other is air. Numerical simulation results of proposed structure indicate that a more uniform surface electric field is obtained and that the vertical electric field in buried oxide is increased. Because the modulation effect of the patterned dielectric on the electric field is in the buried layer and drift region, higher breakdown voltage is achieved in this propose structure than conventional ones.