Title :
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications
Author :
Wang, Chua-Chin ; She, Hsien-Chih ; Hu, Ron
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A CMOS local oscillator using a programmable DLL (delay lock loop)-based frequency multiplier to synthesize carrier frequencies from 1.1 GHz to 1.5 GHz is presented. The frequency of the output clock is 7× to 10× of an input reference clock. No LC-tank is used in the proposed design, such that the power dissipation as well as the active area are drastically reduced. The design is carried out using the TSMC 1P5M 0.25 μm CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the VCDTL (voltage-controlled delay tap line) at the mid point of the working range. Meanwhile, the power dissipation of the physical chip measures only 52.2 mW at 1.2 GHz output.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF oscillators; circuit optimisation; delay lock loops; frequency multipliers; integrated circuit design; integrated circuit measurement; integrated circuit modelling; low-power electronics; programmable circuits; 0.25 micron; 1.1 to 1.5 GHz; 1.2 GHz; 2.5 V; 52.2 mW; CMOS local oscillators; CMOS programmable DLL-based frequency multipliers; LC-tank; LO; VCDTL start-up voltage initialization; carrier frequency synthesis; delay lock loops; input reference clock; optimally shortened average lock time; output clock frequency; power dissipation/active area reduction; power supply voltage; voltage-controlled delay tap lines; wireless applications; working range mid point; CMOS process; Clocks; Delay effects; Frequency locked loops; Frequency synthesizers; Local oscillators; Power dissipation; Power supplies; Tracking loops; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1045335
