• DocumentCode
    242011
  • Title

    Simulation study of a new capacitor-less DRAM with Vertical Nanometer Pillar

  • Author

    Jyun-Min Syu ; Jyi-Tsong Lin ; Chan-Hsiang Chang ; Yu-Chun Wang ; Dai-Rong Lu ; Yong-Huang Lin ; Zih-Hao Huang ; Po-Hsieh Lin

  • Author_Institution
    Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ. (NSYSU EE), Kaohsiung, Taiwan
  • fYear
    2014
  • fDate
    28-31 Oct. 2014
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    In this paper, a novel Vertical Nanometer Pillar structure of Double Gate (VNPDG) capacitor-less DRAM is proposed. The vertical pillar region provides an additional space which can store more excess holes to enhance kink effect easily. Thus, a longer retention time is derived by the virtue of the extend body region perpendicular to the electron inversion channel, which makes the excess holes not be recombined immediately. Combining the virtues of the device with applying the front-gate bias, we can optimize the driving force of drain bias and obtain that the retention time of the new structure is 4.9 × 103 times longer than that of the conventional structure.
  • Keywords
    DRAM chips; VNPDG; capacitor-less DRAM; drain bias; dynamic random access memory; electron inversion channel; front-gate bias; kink effect enhancement; retention time; vertical nanometer pillar structure of double gate; Abstracts; CMOS integrated circuits; CMOS technology; Programming; Random access memory; Standards;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
  • Conference_Location
    Guilin
  • Print_ISBN
    978-1-4799-3296-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2014.7021432
  • Filename
    7021432