Design of SRD-F-PLL system with consideration of low-pass filter for high dynamic performance during voltage disturbance

Usually, LPF (low pass filter) is used in the feedback loop of SRF(Synchronous Reference Frame) - PLL (Phase Locked Loop) system because the measured grid voltage contains harmonic distortions and sensor noises. In this paper, it is shown that the cut-off frequency of the LPF should be designed to suppress the harmonic ripples contained in the measured voltage. Also, a new design method of the loop gain of the PI-type controller in the SRF-PLL is proposed with the consideration of the dynamics of the LPF. As a result, a better transient response can be obtained with the proposed design method. The LPF frequency and PI controller gain are designed in coordination according to the steady state and dynamic performance requirement. This paper shows the feasibility and the usefulness of the proposed methods through the computer simulation and the lab-scale experiments.