Title :
Novel local bit line design based on forced-keeper technique for on-chip memories
Author :
Zezhong Yang ; Jinhui Wang ; Lina Wang ; Ligang Hou ; Na Gong
Author_Institution :
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
Abstract :
A local bit line (LBL) based on forced-keeper technique for on-chip memories is proposed in this paper. The keeper transistor is forced to be turned off adaptively to decrease the leakage current and the contention current to achieve high performance. With SMIC 65 nm technology, the simulation results show that the proposed LBL chosen by the row decoder achieve 89.9% Power-Delay-Produce (PDP) reduction. And the LBL not chosen by row decoder achieve 94.1% and 93.8% power saving with the active clock. The larger memories scale are, the more total power is saved.
Keywords :
clocks; integrated circuit design; integrated memory circuits; leakage currents; low-power electronics; transistor circuits; LBL; PDP reduction; SMIC technology; active clock; contention current; forced-keeper technique; keeper transistor; leakage current; local bit line design; on-chip memories; power saving; power-delay-produce reduction; row decoder; size 65 nm; Abstracts;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021466
