Data mapping scheme and implementation for high-throughput DCT/IDCT transpose memory

In this paper, we proposed a generalized architecture for hardware implementation of the single port SRAM-based transpose memory for large size DCT/IDCT. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A novel data mapping scheme based on the theory of transpose of partitioned matrix is proposed to implement the transpose memory with less SRAM banks. Row access and column access can be perfectly supported under single port SRAM. This design can support DCT/IDCT of different transform sizes with different data throughput rates. Compared with the existed design [4], the proposed design can achieve 44.3% area saving. It is suitable for real-time processing of the video with the resolution up to 7680×4320 UHD.