Title :
Thru-silicon vias for 3D WLP
Author :
Savastionk, S. ; Siniaguine, Oleg ; Korczynski, Ed
Author_Institution :
Tro-Si Technol. Inc., Sunnyvale, CA, USA
Abstract :
Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry
Keywords :
chip scale packaging; integrated circuit interconnections; integrated circuit manufacture; sputter etching; 3D WLP; 3D wafer level packaging; IC manufacturing unit-processes; atmospheric downstream plasma dry chemical etching; manufacturing process flows; robust process flows; thru-silicon interconnections; thru-silicon vias; Chemical technology; Costs; Dry etching; Integrated circuit interconnections; Integrated circuit packaging; Manufacturing processes; Robustness; Silicon; Vacuum technology; Wafer scale integration;
Conference_Titel :
Advanced Packaging Materials: Processes, Properties andInterfaces, 2000. Proceedings. International Symposium on
Conference_Location :
Braselton, GA
Print_ISBN :
0-930815-59-9
DOI :
10.1109/ISAPM.2000.869271
