DocumentCode :
2421039
Title :
Next generation ALIVH substrate for bare chip direct mounting
Author :
Andoh, Daizo ; Sugawa, Toshio ; Nakamura, Tadashi ; Higashitani, Hideki ; Eda, Kazuo ; Tsukamoto, Masahide
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear :
2000
fDate :
2000
Firstpage :
227
Lastpage :
232
Abstract :
The next generation ALIVH(R) substrate named ALIVH(R)-FB substrate was developed. The ALIVH-FB substrate has a structure that fine layers were formed on the surface of the conventional ALIVH substrate. The design rule of the core layer is Line/Space (LIS)=50/50 μm, Via hole diameter/Land diameter (V/L)=120/250 μm and the rule of fine layer is L/S=25/25 μm, V/L=50/150 μm. Three technologies are developed: thin insulator layer by the film material with high heat resistance; fine via hole drilling process by the YAG THG laser and fine interconnection technology using conductive copper paste; and fine layer fabrication by the transfer process. The technologies display the following features: high wiring density by the Fine Via on Via structure; film insulator with high heat resistance and low CTE for a high reliability joint between the bare chip and the substrate; good impedance control for the high frequency circuit; and a flat surface and high heat resistance for the bare chip mounting. The ALIVH-FB substrate is very suitable for the high pin count bare chip direct mounting
Keywords :
fine-pitch technology; integrated circuit packaging; interconnections; microassembling; printed circuit design; substrates; thermal expansion; thermal resistance; 25 to 250 mum; ALIVH-FB substrate; YAG THG laser; any layer inner via hole substrate; bare chip direct mounting; conductive copper paste; core layer design rule; film insulator; fine interconnection technology; fine layer fabrication; fine layer formation; fine layer rule; fine via hole drilling process; fine via on via structure; flat surface; high frequency circuit; high heat resistance; high pin count bare chip direct mounting; high reliability joint; high wiring density; impedance control; line/space ratio; low CTE; next generation ALIVH substrate; thin insulator layer; transfer process; via hole diameter/land diameter ratio; Conducting materials; Conductive films; Drilling; Heat transfer; Insulation; Optical materials; Resistance heating; Space technology; Substrates; Surface resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Packaging Materials: Processes, Properties andInterfaces, 2000. Proceedings. International Symposium on
Conference_Location :
Braselton, GA
Print_ISBN :
0-930815-59-9
Type :
conf
DOI :
10.1109/ISAPM.2000.869276
Filename :
869276
Link To Document :
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