DocumentCode
2421674
Title
Variations of interconnect capacitance and RC delay induced by process fluctuations
Author
Shigyo, Naoyuki
Author_Institution
Syst. LSI Design Div., Toshiba Corp., Yokohama, Japan
fYear
2000
fDate
2000
Firstpage
68
Lastpage
71
Abstract
This article describes the influence of the process fluctuations such as the critical dimension (CD) variation on the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. A new interconnect design guideline to reduce C and/or RC delay variations is proposed
Keywords
capacitance; fluctuations; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; semiconductor process modelling; RC delay; critical dimension variation; fringing capacitance; interconnect capacitance; interconnect design guideline; process fluctuations; tradeoff; Analytical models; Capacitance; Delay; Equations; Fluctuations; Guidelines; Integrated circuit interconnections; Large scale integration; Performance analysis; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Statistical Metrology, 2000 5th International Workshop on
Conference_Location
Honolulu, HI
Print_ISBN
0-7803-5896-1
Type
conf
DOI
10.1109/IWSTM.2000.869314
Filename
869314
Link To Document