High accuracy CMOS capacitance multiplier

This paper presents a CMOS circuit suitable to magnify the value of a grounded unit capacitance. The multiplication factor is achieved through the gain of current mirrors and its maximum value is solely limited by power consumption constraints. Circuit solutions are then developed to reduce power dissipation and to enable the detection of small unit capacitances. Thanks to its inherent simplicity, the circuit is also characterized by wide-band operations. An on-chip tuning technique is also included which allows the value of the obtained capacitance to be adjusted by about 70%. Simulations of a design example are provided.