Title :
Investigation of layout effect on ESD performance of SCR-nLDMOS devices
Author :
Yang Wang ; Xiangliang Jin ; Huihui Yuan ; Qi Jiang ; Liu Yang
Author_Institution :
Fac. of Mater., Optoelectron. & Phys., Xiangtan Univ., Xiangtan, China
Abstract :
A robust ESD device for 5V circuit protection was designed and fabricated in a 0.5-μm 5V/18V CDMOS process. It is composed of paralleled SCR and nLDMOS. The ESD performance of multi-fingered SCR-nLDMOS devices with strip and segment SCR layout style is investigated by employing transmission line pulse (TLP) measurement. The SCR-nLDMOS with strip SCR is superior to SCR-nLDMOS applying segment SCR for its relatively stronger ESD current handling capability of 1.42mA/μm2, which is also much higher than that of traditional gate-grounded 5V NMOS (1.04mA/μm2). The SCR-nLDMOS with segment SCR provides us an option to elevate Vh from 2.9V up to 5.7V.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; thyristors; CDMOS process; ESD device; TLP measurement; circuit protection; multifingered SCR-nLDMOS devices; paralleled SCR; segment SCR layout style; size 0.5 mum; strip SCR layout style; transmission line pulse measurement; voltage 18 V; voltage 5 V; Abstracts; Anodes; Cathodes; Discharges (electric); Electrostatic discharges; Layout; Robustness;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021539
