• DocumentCode
    24223
  • Title

    Nanowire-Based Anisotropic Conductive Film: A Low Temperature, Ultra-fine Pitch Interconnect Solution.

  • Author

    Jing Tao ; Mathewson, Alan ; Razeeb, Kafil M.

  • Author_Institution
    Tyndall Nat. Inst., Univ. Coll. Cork, Cork, Ireland
  • Volume
    9
  • Issue
    1
  • fYear
    2015
  • fDate
    Mar-15
  • Firstpage
    4
  • Lastpage
    11
  • Abstract
    Advanced microelectronics packaging, driven by the multiple benefits of system performance, power, size, and cost, has now entered the three-dimensional (3-D) era. According to the International Technology Roadmap for Semiconductors 2012 [1], the interconnect pitch size is predicted to be 4-16 μm at the global interconnect level by the year 2018. Silicon die incorporated with through-silicon-via (TSV) technology [2] can be stacked using solder microbumps as high-density interconnects [3]. However, solder microbump technology faces many challenges because of the intermetallic compound growth and an underfill requirement as the bump size reduces [4]. Meanwhile, the temperature of the soldering process is more than 260 oC, which can result in high thermal stress in the devices and impact the thermal budget of the processing, particularly for the multitechnology node-stacking processes [5]. Therefore, developing interconnect methods, which can provide ultrafine-pitch capability and low-temperature process for 3-D systems, attracts continuous attention from industry [6].
  • Keywords
    integrated circuit interconnections; integrated circuit packaging; low-temperature techniques; soldering; solders; thermal stresses; three-dimensional integrated circuits; 3D systems; TSV technology; advanced microelectronics packaging; global interconnect level; high-density interconnects; interconnect pitch size; intermetallic compound growth; low temperature ultra-fine pitch interconnect solution; low-temperature process; multitechnology node-stacking processes; nanowire-based anisotropic conductive film; silicon die; size 4 mum to 16 mum; solder microbump technology; soldering process; thermal budget; thermal stress; three-dimensional era; through-silicon-via; Bonding; Bonding forces; Intermetallic; Microelectronics; Microfabrication; Nanowires; Polymers; Surface treatment; System performance; Thermal stresses; Through-silicon vias;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    1932-4510
  • Type

    jour

  • DOI
    10.1109/MNANO.2014.2373531
  • Filename
    7012076