On the scalability of joint channel and mismatch estimation for time-interleaved analog-to-digital conversion in communication receivers

The analog-to-digital converter (ADC) represents a fundamental bottleneck in power- and cost-efficient realizations of “mostly digital” communication transceivers at multi-Gigabit speeds. Time-interleaved (TI) ADCs, with slower, power-efficient “sub-ADCs” employed in parallel to obtain a high-rate ADC, represent a potential solution to this bottleneck. The performance floor caused by mismatch in TI-ADCs can be eliminated by estimating and correcting for the mismatch. For TI-ADCs employed in communication receivers, prior work has shown that mismatch and channel parameters can be estimated jointly by using the training available in communication systems. In this paper, we propose simplified algorithms for this purpose, and examine how well they scale as the number of sub-ADCs gets large. We conclude that rapid convergence can be attained if the training sequence scales with the number of sub-ADCs, and that the convergence rate can be significantly enhanced by a suitable choice of periodic training sequence.