• DocumentCode
    2422398
  • Title

    Coprocessor Computing with FPGA and GPU

  • Author

    Park, Song Jun ; Shires, Dale R. ; Henz, Brian J.

  • Author_Institution
    Aberdeen Proving Ground, US Army Res. Lab. (ARL), Aberdeen, MD
  • fYear
    2008
  • fDate
    14-17 July 2008
  • Firstpage
    366
  • Lastpage
    370
  • Abstract
    Specialized secondary processing units, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), attempt to tackle the time consuming applications containing high computational requirements. In order to achieve acceleration, FPGAs allow a customizable architecture and Nvidia GPUs offer up to 16 cores with 128 stream processors. The following research presents the experiences of designing integer and floating-point based algorithms for Xilinx FPGAs and programming on NVIDIA graphics card. For test case applications, an encryption function and a sorting algorithm were investigated. The implementation of an encryption algorithm depicts the performance results of an integer application composed of bit operations and a simple sort algorithm tests the effects of a floating-point application containing large numbers of multiple independent sorting instructions.
  • Keywords
    computer graphic equipment; coprocessors; cryptography; field programmable gate arrays; floating point arithmetic; Nvidia GPU; Xilinx FPGA; coprocessor computing; customizable architecture; encryption algorithm; field programmable gate arrays; floating-point based algorithms; graphics processing units; Acceleration; Algorithm design and analysis; Computer applications; Computer architecture; Coprocessors; Cryptography; Field programmable gate arrays; Graphics; Sorting; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    DoD HPCMP Users Group Conference, 2008. DOD HPCMP UGC
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-3323-0
  • Type

    conf

  • DOI
    10.1109/DoD.HPCMP.UGC.2008.69
  • Filename
    4755892