A low kickback noise and offset calibrated dynamic comparator for 2B/C SAR ADC

A low kickback noise and offset calibrated dynamic comparator used in a high speed capacitive 2-bit-per-cycle (2b/C) SAR ADC was presented. This paper discusses the sources of kickback noise and offset voltage of the dynamic comparator. And then the proposed comparator decreases the kickback noise to the range without affecting the performance of comparator. The next, a calibration unit is shown to decrease the offset voltage to σ± 0.5 mV with the range σ± 16 mV to meet the demand of the 8-b 2b/C SAR ADC. The proposed comparator is composed and simulated in 65 nm technology. The proposed comparator has 0.01 mV kickback noise at 7.9 mV differential input voltage and the calibration unit could calibrate the offset to -0.4±0.5 mV at 66 times Monte-Carlo simulations.