Title :
Design of compact CN delay-based PUFS in 65nm CMOS
Author :
Yuejun Zhang ; Pengjun Wang ; Jianrui Li ; Gang Li
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
Abstract :
Physical Unclonable Functions (PUFs) exploit the statistical variation of CMOS circuit during manufacture process to generate unclonable secret data. In the paper, compact C2n delay-based PUFs (C2n -PUFs) is designed in TSMC 65nm CMOS technology. After configuring the delay-paths, C2n-PUFs build different data without circuit replace. C2n combination method exponential decreases the number of delay path with keeping the output data bits. In custom designed, the area of 128-bit C2n -PUFs is 30 × 147μm2. Experimental results show that the C2n -PUFs have reliability and randomness features, and improve information density about 89.6%.
Keywords :
CMOS logic circuits; delay circuits; integrated circuit design; statistics; CMOS circuit; TSMC CMOS technology; delay paths; delay-based PUF; information density; physical unclonable functions; size 147 mum; size 30 mum; size 65 nm; statistical variation; unclonable secret data; CMOS integrated circuits; CMOS process; Delays; Layout; Reliability; Semiconductor device modeling;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021557