Charge pump based PLL design for IEEE 1394b PHY

Author

Qiang Lu ; HaiQi Liu ; Qiang Li

Author_Institution

Integrated Syst. Lab., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

This work describes a charge pump based phase-locked loop (PLL) employed in IEEE 1394b physical (PHY) system. The proposed PLL has a third order, type-2 topology, and its voltage-controlled oscillator (VCO) is composed of 4-stage delay cells to provide four phases of 1-GHz signals. This PLL has been fabricated in a 0.13-μm CMOS technology with 1.2V power supply voltage. According to the measurement results, the locking time is less than 5 μs, the peak-peak jitter and the RMS jitter are 398ps and 60ps, respectively. The die area of the PLL is 0.12mm², and the total power consumption is 19mW.

Keywords

CMOS analogue integrated circuits; IEEE standards; charge pump circuits; phase locked loops; voltage-controlled oscillators; 4-stage delay cells; CMOS technology; IEEE 1394b PHY; VCO; charge pump based PLL design; frequency 1 GHz; phase-locked loop; physical system; power 19 mW; size 0.13 mum; time 398 ps; time 60 ps; type-2 topology; voltage 1.2 V; voltage-controlled oscillator; Abstracts; Charge pumps; Phase locked loops; Voltage-controlled oscillators; IEEE 1394b; Phase-locked loop (PLL); multi-phase VCO;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021560

Filename

7021560