Title :
Modeling requirements for computer-aided VLSI circuit reliability assessment
Author :
Sheu, Bing J. ; Hsu, Wen-jay ; Tyree, Vance C.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
It is noted that challenges to the improvement of quality and reliability in VLSI circuits come from the rapid advances of CMOS fabrication technologies. To provide circuit designers with the means for designing circuits that can utilize the full reliability potential of the fabrication technology, a circuit reliability simulator has been developed. Key reliability concerns in VLSI circuits and microsystems include hot-carrier damage, electromigration, time-dependent dielectric breakdown, packaging damage, radiation damage, and contamination of oxides and junctions. The authors describe several salient modeling requirements for reliability simulations at the detailed circuit design level using the SPICE circuit simulator as the key module
Keywords :
CMOS integrated circuits; MOS integrated circuits; VLSI; circuit analysis computing; circuit reliability; semiconductor device models; CMOS fabrication; MOS transistors; SPICE; VLSI circuit; circuit design level; circuit reliability simulator; computer aided technique; electromigration; hot-carrier damage; junction contamination; modeling requirements; oxide contamination; packaging damage; radiation damage; reliability assessment; time-dependent dielectric breakdown; CMOS technology; Circuit simulation; Contamination; Dielectric breakdown; Electromigration; Fabrication; Hot carriers; Packaging; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth
Conference_Location :
Westborough, MA
DOI :
10.1109/UGIM.1989.37335