A high speed vision processor for chip package visual inspection

This paper proposes a high speed vision processor for chip package defect visual inspection. The processor includes a 64×64 pixel-parallel processing elements (PE) array, 64 row-parallel processors (RP) array and a dual core RISC. It adopts massively parallel single instruction multiple data (SIMD) architecture and can perform vision processing algorithms in multiple parallel fashions. The developed algorithms for chip package inspection can be implemented by the vision processor effectively. Experimental results show that it can successfully find out defects of the cover tape and longer pin at a rate of 80 products per second, which is much faster than traditional systems.