VLSI implementation of a CORDIC SVD processor

Author

Cavallaro, Joseph R. ; Keleher, Michael P. ; Price, Russell H. ; Thomas, Gregory S.

Author_Institution

Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA

fYear

1989

fDate

12-14 Jun 1989

Firstpage

256

Lastpage

260

Abstract

The design and custom CMOS VLSI implementation of a CORDIC SVD (singular-value decomposition) processor is presented. Special-purpose parallel processor arrays have many important applications in real-time signal processing. The processor architecture is reviewed and the current CORDIC Z-control and X,Y data path chips are described. Current work includes the expansion of the 10-bit CORDIC Z-control chip to a 20-bit design to complement the CORDIC X,Y data path design. The hierarchical design methodology will lead next to a full CORDIC processor followed by a complete CORDIC SVD processor and array

Keywords

CMOS integrated circuits; VLSI; computerised signal processing; digital signal processing chips; parallel architectures; real-time systems; 10 bit; 16 bit; 20 bit; CORDIC SVD processor; DSP chips; VLSI implementation; X/Y data path chips; Z-control chip; custom CMOS; hierarchical design methodology; parallel processor arrays; processor architecture; real-time signal processing; singular-value decomposition; Application software; Array signal processing; CMOS process; Computer architecture; Design engineering; Design methodology; Matrix decomposition; Signal processing algorithms; Singular value decomposition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth

Conference_Location

Westborough, MA

ISSN

0749-6877

Type

conf

DOI

10.1109/UGIM.1989.37346

Filename

37346