10-bit 20MS/S differential SAR ADC for image sensor

Low-power and small-area implementations are essential in the CMOS image sensor market. At the same time, to achieve high-accuracy and high-speed is very important for ADC studying. This paper presents the design of a 10-bit 20MS/s differential Successive Approximation Register (SAR) ADC with a new switching procedure using for CMOS image sensor application. Compared with conventional 10-bit ADC, the number of capacitors is reduced by 50% and the average switching energy consumption is reduced by 81.26%. The ADC is fabricated in 0.18um CMOS technology and occupies an active area of 750×135um². The ADC shows a SNDR of 61.33dB, a SFDR of 77.09dB, and an ENOB of 9.89bits with a 566.4KHz sinusoidal input at 20MS/s sampling frequency. The ADC consumes about 750uW at 1.8V supply.