Use of A*N+B codes for fault-tolerant bit-serial array processors

An approach to error detection in bit-serial array processors based on coding is presented. The optimal choice of such a code is also discussed. Methodologies to design array processors with high error-detection capability, low silicon area consumption, and low computational overhead are proposed and evaluated. A*N+B coding is considered both at a local and array level. In the first case each processor element is tested to detect errors; in the second case the check on the results is performed only at the outputs of the whole array.<>