• DocumentCode
    2423205
  • Title

    Energy-Performance Tradeoffs in Software Transactional Memory

  • Author

    Baldassin, Alexandro ; De Carvalho, João P L ; Garcia, Leonardo A G ; Azevedo, Rodolfo

  • Author_Institution
    UNESP - Univ. Estadual Paulista, Rio Claro, Brazil
  • fYear
    2012
  • fDate
    24-26 Oct. 2012
  • Firstpage
    147
  • Lastpage
    154
  • Abstract
    Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads.
  • Keywords
    multiprocessing systems; parallel programming; power aware computing; software performance evaluation; storage management; transaction processing; DVFS-based technique; DVFS-enhanced policy; EDP reduction; STAMP workload; computer system; conflict resolution scheme; dynamic voltage and frequency scaling; energy consumption; energy tradeoff; energy-delay product; energy-performance tradeoff; lock-based STM algorithm; multicore processor; parallel programming; resolution policy; runtime performance; runtime tradeoff; software implementation; software transactional memory system; synchronization mechanism; Algorithm design and analysis; Bioinformatics; Delay; Energy consumption; Genomics; Program processors; Energy Consumption; Parallel Computing; Transactional Memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on
  • Conference_Location
    New York, NY
  • ISSN
    1550-6533
  • Print_ISBN
    978-1-4673-4790-7
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2012.19
  • Filename
    6374783