A shared-memory multiprocessor logic simulator

Author

Beihl, Gary

Author_Institution

Microelectron. Comput. Technol. Corp., Austin, TX, USA

fYear

1989

fDate

22-24 March 1989

Firstpage

26

Lastpage

28

Abstract

A simple multiprocessor logic simulation kernel is described and preliminary benchmark results presented. Communication between processors is through shared global memory, with locking/unlocking provided by the host operating system. Partitioning the gate evaluation list and current event queue among processors gives a dynamic self-balancing effect which tends to evenly distribute the load associated with large simulations. The kernel is written entirely in C and currently runs on a Balance 8000 system under the DYNIX 2.1 operating system. For a 3800-gate combinational circuit, 90% efficiency is achieved for a two-processor simulation.<>

Keywords

combinatorial circuits; logic CAD; multiprocessing systems; performance evaluation; Balance 8000 system; C; DYNIX 2.1 operating system; benchmark results; combinational circuit; current event queue; dynamic self-balancing effect; gate evaluation list; host operating system; locking; partitioning; shared-memory multiprocessor logic simulator; two-processor simulation; unlocking; Circuit simulation; Computational modeling; Data structures; Discrete event simulation; Kernel; Logic; Operating systems; Partitioning algorithms; Processor scheduling; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on

Conference_Location

Scottsdale, AZ, USA

Print_ISBN

0-8186-1918-x

Type

conf

DOI

10.1109/PCCC.1989.37354

Filename

37354