A 32×32B 65NM 4R/2W register file for low-power operation

This paper describes a 32×32b 4R/2W (4 read ports and 2 write ports) register file for low power operation in 65 nm CMOS. A new separated read port with four transistors is proposed to reduce the bit line leakage during read mode. Compared to previous 1P3N read port design, it has smaller area and better performance with almost no penalty in leakage current. In addition, two extra transistors are added to cut off the feedback between the two inverters during write mode. This results in an obvious improvement in write noise margin. Moreover, the cell array is divided into two banks with each bank 16 words. In this way, the capacity on the local read bit line is reduced to 50% of that not banked, which reduces power consumption further. According to the post-layout simulation results, the read latency is 506ps and 60.8ns at 1.2V and 0.4V respectively.