• DocumentCode
    2423595
  • Title

    Development of digital experiment system for multi-module-cascaded multilevel high-power inverter

  • Author

    Jinghua, Zhou ; Yaai, Chen ; Lanya, Yao ; Zhengxi, Li

  • Author_Institution
    Power Electron. & Motor Driver Eng. Center, North China Univ. of Technol., Beijing, China
  • fYear
    2009
  • fDate
    17-20 May 2009
  • Firstpage
    1613
  • Lastpage
    1617
  • Abstract
    Based on a multi-module-cascaded multilevel inverter structure for the optimization of harmonics, this paper introduces a horizontal phase-shifting sinusoidal pulse width modulation (SPWM) strategy applied to multi-module-cascaded inverter, and at the same time, based on digital signal processor (DSP) and complex programmable logic device (CPLD), this paper also presents a digital algorithm for horizontal phase-shifting SPWM modulation, which has solved the problem of the exactly lock of each triangular carrier phase in the multi-module-cascaded system. The simulation and experimental results have proven the method proposed correct.
  • Keywords
    PWM invertors; digital signal processing chips; optimisation; power conversion harmonics; programmable logic devices; CPLD; DSP chip; complex programmable logic device; digital signal processor; horizontal phase-shifting sinusoidal pulse width modulation strategy; multimodule-cascaded multilevel high-power inverter; optimization; Digital control; Digital modulation; Digital signal processing; Frequency; Modulation coding; Phase modulation; Power electronics; Pulse inverters; Pulse width modulation inverters; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Electronics and Motion Control Conference, 2009. IPEMC '09. IEEE 6th International
  • Conference_Location
    Wuhan
  • Print_ISBN
    978-1-4244-3556-2
  • Electronic_ISBN
    978-1-4244-3557-9
  • Type

    conf

  • DOI
    10.1109/IPEMC.2009.5157647
  • Filename
    5157647