Design of a wideband digitally controlled oscillator

Author

Junhui Xiang ; Lei Ma ; Linghao Zhu ; Hao Min

Author_Institution

Sch. of Microelectron., Fudan Univ., Shanghai, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

This paper presents a wide-band digitally controlled oscillator (DCO) applied in all digital phase locked loop (ADPLL) of which the tuning range is 3GHz-5.3GHz. Capacitor tank of the oscillator contains 3 major arrays: coarse tuning bank, medium tuning bank and fine tuning bank (including fractional tuning capacitors), which are all formed by varactors. Post-layout simulation is done to verify its performance on SMIC 40nm process. The oscillator phase noise is -137dBc/Hz at 3MHz, 3.7GHz, and power consumption is 8.6mW and 7mW respectively where center frequency is 3GHz and 5.3GHz.

Keywords

CMOS digital integrated circuits; digital circuits; field effect MMIC; microwave oscillators; phase locked loops; SMIC process; all digital phase locked loop; coarse tuning bank; fine tuning bank; fractional tuning capacitors; frequency 3 GHz to 5.3 GHz; medium tuning bank; post layout simulation; size 40 nm; wideband digitally controlled oscillator; Abstracts; Detectors; Educational institutions; Equations; Inductors; Oscillators; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021606

Filename

7021606