Notice of Violation of IEEE Publication PrinciplesFully-Integrated 0.13 μm CMOS Digital Low-IF DVB-S/S2 Satellite TV Tuner Using a Discrete-Step AGC Loop

Notice of Violation of IEEE Publication Principles

"Fully-Integrated 0.13 μm CMOS Digital Low-IF DVB-S S2 Satellite TV Tuner Using a Discrete-Step AGC Loop"
by Maxim, A.; Poorfard, R.; Johnson, R.; Crawley, P.; Kao, J.; Dong, Z.; Chennam, M.; Nutt, T.; Trager, D.;
in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,
Jan. 2007 Page(s):67 - 70

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici D. Smith S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A fully-integrated digital low-IF DVB-S/DVB-S2 satellite TV tuner was realized in 0.13 μm CMOS. It uses a first analog down-conversion to a sliding low-IF, followed by digitization, a second digital mixing to baseband and digital channel selection. Performing more signal processing in the digital domain lead to a relaxation of the RF front-end specifications, allowing its CMOS implementation. The digital low-IF architecture provides a digital power estimation and allows the use of a discrete-step AGC loop that results in a lower n- oise and linearity degradation in comparison with continuous AGC loops. Digital calibration is used throughout the DVB tuner, minimizing the gain variation over corners and relaxing the noise and linearity constraints. Partitioning the DVB-S2 receiver into a front-end tuner IC built in a mixed-signal CMOS process and a back-end demodulator and MPEG processor IC implemented in a straight digital CMOS process minimizes the receiver cost