Design and implementation of fefet-based lookup table

Ferroelectric random access memory (FeRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design due to its high density, high speed operation, anti-radiation and non-volatility. Ferroelectric gate field effect transistors (FeFETs) have been extensively studied and its usage in memory elements and basic analog circuit configurations has gained much interests. Here, we propose a novel architecture of FeFET-based LUT. An improved timing mode of FeRAM chip is analyzed to satisfy the performance of the FeFET-based LUT. Decoder, driver circuit and sensitive amplifier for FeFET array are also proposed. Every design process is simulated by Sentarus TCAD. All the simulation results show that the proposed LUT works properly when the frequency reaches 500 MHz at 0.3 V differential input.