High Performance Connected Components Labeling on FPGA

Author

Grana, Costantino ; Borghesani, Daniele ; Santinelli, Paolo ; Cucchiara, Rita

Author_Institution

Univ. degli Studi di Modena e Reggio Emilia, Modena, Italy

fYear

2010

fDate

Aug. 30 2010-Sept. 3 2010

Firstpage

221

Lastpage

225

Abstract

This paper proposes a comparison of the two most advanced algorithms for connected components labeling, highlighting how they perform on a soft core SoC architecture based on FPGA. In particular we test our block based connected components labeling algorithm, optimized with decision tables and decision trees. The embedded system is composed of the CMOS image sensor, FPGA, DDR SDRAM, USB controller and SPI Flash. Results highlight the importance of caching and instructions and data cache sizes for high performance image processing tasks.

Keywords

CMOS image sensors; decision tables; decision trees; embedded systems; field programmable gate arrays; image processing; system-on-chip; CMOS image sensor; DDR SDRAM; SPI Flash; USB controller; connected components labeling algorithm; data cache sizes; decision tables; decision trees; embedded system; field programmable gate array; high performance image processing tasks; soft core SoC architecture; system-on-chip; Computer architecture; Decision trees; Field programmable gate arrays; Labeling; Pixel; Random access memory; Universal Serial Bus; CMOS image sensor; FPGA; connected components labeling; system on chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Database and Expert Systems Applications (DEXA), 2010 Workshop on

Conference_Location

Bilbao

ISSN

1529-4188

Print_ISBN

978-1-4244-8049-4

Type

conf

DOI

10.1109/DEXA.2010.57

Filename

5592081