DocumentCode
2424672
Title
Chip multithreading: opportunities and challenges
Author
Spracklen, Lawrence ; Abraham, Santosh G.
Author_Institution
Scalable Syst. Group, Sun Microsystems Inc., Sunnyvale, CA, USA
fYear
2005
fDate
12-16 Feb. 2005
Firstpage
248
Lastpage
252
Abstract
Chip multi-threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including simultaneous multithreading (SMT) and chip multiprocessing (CMP). CMT processors are especially suited to server workloads, which generally have high levels of thread-level parallelism (TLP). In this paper, we describe the evolution of CMT chips in industry and highlight the pervasiveness of CMT designs in upcoming general-purpose processors. The CMT design space accommodates a range of designs between the extremes represented by the SMT and CMP designs and a variety of attractive design options are currently unexplored. Though there has been extensive research on utilizing multiple hardware threads to speed up single-threaded applications via speculative parallelization, there are many challenges in designing CMT processors, even when sufficient TLP is present. This paper describes some of these challenges including, hot sets, hot banks, speculative prefetching strategies, request prioritization and off-chip bandwidth reduction.
Keywords
microprocessor chips; multi-threading; multiprocessing systems; parallel architectures; CMP design; CMT chips; CMT design; CMT processors; SMT design; chip multi-threaded processors; chip multiprocessing; chip multithreading; simultaneous multithreading; thread-level parallelism; Bandwidth; Delay; Hardware; Multithreading; Out of order; Parallel processing; Pipelines; Process design; Surface-mount technology; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on
ISSN
1530-0897
Print_ISBN
0-7695-2275-0
Type
conf
DOI
10.1109/HPCA.2005.10
Filename
1385946
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