Abstract :
The integration of on-chip monitors that monitor a variety of chip parameters like temperature; process corner, etc. are finding increasing use in modern day SOCs and Microprocessors. Such monitors are used for optimizing various performance measures as well as for device characterization. With newer processes the challenge is of designing reliable ICs from inherently unreliable components. More specifically designers have to address the issue of extreme process variation and time-dependent aging. New on-chip design techniques to characterize the manufacturing and time-dependent variation sources of a chip have been proposed. This special session will present three papers dealing with this topic. The first will discuss test structures for characterizing variations in narrow-width devices that adversely affect SRAM reliability. Application of variation characterization to post-silicon repair of SRAM will be presented along with silicon results from test chips. The second paper will discuss a number of “silicon odometer” designs that we have implemented in order to measure circuit degradation caused by front-end-of-line reliability mechanisms such as Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB). The third paper will present silicon results from a 90nm and 65nm production design that tries to ascertain the accuracy of on-chip monitors in current designs vis-à-vis more direct measurement techniques like manufacturing testing. An analysis of the results for using on-chip monitors to match dies for 3D-applications or system integration will be presented.
