VDDmin test optimization for overscreening minimization through adaptive scan chain masking

Very-low-voltage (VDDmin) test assumes significant importance in detecting flaws in marginal chips as it can magnify the electrical impact of flaws. Yet such a test scheme is increasingly sensitive to test mode IR-drop. Exceedingly high test mode current and voltage surge may result in good chips failing VDDmin test, thus resulting in yield loss. A technique to counteract such yield loss, scan chain masking, has been widely incorporated in commercial DFT tools to address this issue. However, the masking of scan cells might lead to a reduced flaw coverage, necessitating a thorough investigation of its impact on test quality during the development of the optimal test plan. In this paper, we propose an analytical model to evaluate the cost of scan chain masking in terms of test escapes and overscreening effect. An adaptive scan chain masking flow guided by this model is then proposed to enhance the VDDmin test effectiveness in terms of the overall cost. The proposed flow adaptively identifies the IR-drop sensitive scan chains through the use of silicon debugging data of known-good parts and/or IR-drop simulation results, thus effectively avoiding the overmasking of scan chains that do not contribute to test mode IR-drop failures. This flow additionally delivers rapid convergence to a scan chain masking scheme that minimizes the overall escape/overscreening cost, thus significantly reducing engineering time in silicon debugging. Experimental results on real silicon confirm that the proposed methodology drastically reduces overscreening of good parts at negligible impact on test quality.