Title :
SENSS: security enhancement to symmetric shared memory multiprocessors
Author :
Zhang, Youtao ; Gao, Lan ; Yang, Jun ; Zhang, Xiangyu ; Gupta, Rajiv
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Dallas, TX, USA
Abstract :
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of attacks. This paper proposes a security enhancement model called SENSS, that allows programs to run securely on a symmetric shared memory multiprocessor (SMP) environment. In SENSS, a program, including both code and data, is stored in the shared memory in encrypted form but is decrypted once it is fetched into any of the processors. In contrast to the traditional uniprocessor XOM model (Lie et al., 2000), the main challenge in developing SENSS lies in the necessity for guarding the clear text communication between processors in a multiprocessor environment. In this paper we propose an inexpensive solution that can effectively protect the shared bus communication. The proposed schemes include both encryption and authentication for bus transactions. We develop a scheme that utilizes the cipher block chaining mode of the advanced encryption standard (CBC-AES) to achieve ultra low latency for the shared bus encryption and decryption. In addition, CBC-AES can generate integrity checking code for the bus communication over time, achieving bus authentication. Further, we develop techniques to ensure the cryptographic computation throughput meets the high bandwidth of gigabyte buses. We performed full system simulation using Simics to measure the overhead of the security features on a SMP system with a snooping write invalidate cache coherence protocol. Overall, only a slight performance degradation of 2.03% on average was observed when the security is provided at the highest level.
Keywords :
block codes; cryptography; message authentication; shared memory systems; system buses; transaction processing; SENSS model; SMP system; advanced encryption standard; bus transaction authentication; bus transaction encryption; cache coherence protocol; cipher block chaining mode; cryptographic computation; high performance multiprocessor enterprise server; integrity checking code; multiprocessor environment; security enhancement; shared bus communication; shared bus decryption; shared bus encryption; symmetric shared memory multiprocessor; text communication; Authentication; Bandwidth; Computational modeling; Cryptography; Data security; Delay; Performance evaluation; Protection; Standards development; Throughput;
Conference_Titel :
High-Performance Computer Architecture, 2005. HPCA-11. 11th International Symposium on
Print_ISBN :
0-7695-2275-0
DOI :
10.1109/HPCA.2005.31