DocumentCode :
2424986
Title :
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling
Author :
Huang, Xuan-Lun ; Huang, Jiun-Lang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2010
fDate :
19-22 April 2010
Firstpage :
289
Lastpage :
294
Abstract :
This paper presents a loopback methodology for static linearity testing of an ADC/DAC pair; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the needed test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.
Keywords :
analogue-digital conversion; circuit testing; digital-analogue conversion; ADC-DAC loopback testing methodology; DAC output offsetting; static linearity testing; Analog-digital conversion; Automatic testing; Bandwidth; Data conversion; Electronic equipment testing; Histograms; Linearity; Multimedia communication; System testing; Very large scale integration; ADC/DAC testing; design-fortest; loopback testing; mixed-signal testing; segmented current-steering DAC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2010 28th
Conference_Location :
Santa Cruz, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4244-6649-8
Type :
conf
DOI :
10.1109/VTS.2010.5469548
Filename :
5469548
Link To Document :
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