DocumentCode :
2425036
Title :
On-line configuration of a time warp parallel discrete event simulator
Author :
Radhakrishnan, Radharamanan ; Abu-Ghazaleh, Nael ; Chetlur, Malolan ; Wilsey, Philip A.
Author_Institution :
Dept. of Electr. Comput. & Eng. Comput. Sci., Comput. Archit. Design Lab., Cincinnati, OH, USA
fYear :
1998
fDate :
10-14 Aug 1998
Firstpage :
28
Lastpage :
35
Abstract :
In time warp simulations, the overheads associated with rollbacks, state-saving and the communication induced by rollbacks are the chief contributors to the cost of the simulation; thus, these aspects of the simulation have been primary targets for optimizations. Unfortunately, the behavior of the time warp simulation is highly dynamic and greatly influenced by the application being simulated. Thus, the suggested optimizations are only effective for certain intervals of the simulation. This paper argues that the performance of time warp simulators benefits from a dynamic on-line decision process that selects and configures the sub-algorithms implementing the different aspects of the simulator to best match the current behavior of the simulation. In particular we study control strategies to dynamically: (i) adjust the checkpointing (or state-saving) interval (ii) select the cancellation strategy (lazy or aggressive), and (iii) determine the policy for aggregating the application messages (an optimization that significantly improves the performance in message passing environments). The strategies have been implemented in the WARPED time warp simulation kernel and the performance obtained via the dynamically controlled optimizations is shown to surpass that of their best performing static counterparts
Keywords :
message passing; parallel algorithms; performance evaluation; time warp simulation; WARPED time warp simulation kernel; application messages; checkpointing; control strategies; dynamically controlled optimizations; message passing environments; online configuration; optimizations; performance evaluation; rollbacks; time warp parallel discrete event simulator; Computational modeling; Computer architecture; Cost function; Design optimization; Discrete event simulation; Kernel; Laboratories; Message passing; Read only memory; Time warp simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing, 1998. Proceedings. 1998 International Conference on
Conference_Location :
Minneapolis, MN
ISSN :
0190-3918
Print_ISBN :
0-8186-8650-2
Type :
conf
DOI :
10.1109/ICPP.1998.708460
Filename :
708460
Link To Document :
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